6-layer board design scheme and skills

     With the increase of circuit complexity, the design of PCB boards is also developing in the direction of high density and high requirements. The application of six-layer boards is also becoming more and more widespread. For example, the PCB board of the memory module , starting from PC100, clearly stipulates that at least six-layer board structure must be used. Because multilayer boards are significantly better than low-layer PCB boards in terms of electrical characteristics, suppression of electromagnetic radiation, and ability to resist physical and mechanical damage. 
There are two types of typical six-layer board structures: one is that the surface layer and the bottom layer are not adjacent to the reference plane, and there are certain difficulties in impedance control. It is necessary to increase the line width or increase the thickness of the sinking copper to meet the design impedance requirements; One is that each signal layer has a close reference plane adjacent to it, the impedance is easy to control, and it is also beneficial to suppress crosstalk and electromagnetic radiation. The coupling between power supply and ground can be improved through effective bypass capacitor design. The six-layer board structure is shown in the figure below.

     Scheme 1: The number of power layers is 1, the number of ground layers is 1, and the number of signal layers is 4, as shown in the figure below. From the perspective of impedance control, this arrangement is reasonable, but because the power supply is far away from the ground plane, it is not very effective in reducing the radiation of common-mode EMI.

     Solution 2: The number of power supply layers is 1, the number of ground layers is 1, and the number of signal layers is 4, as shown in the figure below.

     Scheme 3: The number of power supply layers is 1, the number of ground layers is 2, and the number of signal layers is 3, as shown in the figure below.

     No matter from the perspective of impedance control or EMI reduction, the environment required for high-speed signal integrity design can be realized. The disadvantage is that the layer stacking is unbalanced. The third layer is the signal wiring layer, and the corresponding fourth layer is a large-area copper-clad power layer, which may cause problems in process manufacturing. In the design, the third layer can be coated with copper to achieve an approximately balanced effect.
     Solution 4: The number of power supply layers is 1, the number of ground layers is 2, and the number of signal layers is 3, as shown in the figure below. 
     
     For the six-layer board, the priority is scheme 3, preferably the wiring layer S2 (signal 2), followed by S3 (signal 3), S1 (signal 1). The main power supply and its corresponding ground wiring are on the 4th and 5th layers. When setting the layer thickness, increase the distance between S2 (signal 2) and P (power supply), and reduce the distance between P (power supply) and G2 (ground 2). The distance between (correspondingly reduce the distance between G1 (ground 1) and S2 (signal 2) layers) to reduce the impedance of the power plane and reduce the impact of power on S2 (signal 2). When the cost requirement is high, scheme 1 can be adopted, preferably wiring layer S1 (signal 1), S2 (signal 2), followed by S3 (signal 3), S4 (signal 4), compared with scheme 1, scheme 2 Ensure that the power and ground planes are adjacent, reducing the impedance of the power supply, but S1 (signal 1), S2 (signal 2), S3 (signal 3), S4 (signal 4) are all exposed outside, only S2 (signal 2 ) to have a better reference plane. For occasions with high local and small signal requirements, scheme 4 is more suitable than scheme 3,and it can provide excellent wiring layer S2 (signal 2).