With the working frequency of devices becoming increasingly high, the signal integrity and other issues faced in high-speed PCB design have become a bottleneck in traditional design. Engineers are facing increasing challenges in designing a complete solution. Although relevant high-speed simulation tools and interconnection tools can help designers solve some difficulties, high-speed PCB design also requires more and more experience accumulation and in-depth communication within the industry.
The influence of pads on high-speed signals
In a PCB, from a design perspective, a via mainly consists of two parts: the drilling in the middle and the pad around the drilling. The pad has an impact on high-speed signals, similar to the impact of a device's package on the device. A detailed analysis is that after the signal comes out of the IC, it passes through the bonding wire, pins, package shell, pad, and solder to reach the transmission line. All the joints in this process will affect the quality of the signal. But in actual analysis, it is difficult to give specific parameters of the pad, solder, and pins. Therefore, generally, the parameters of the package in the IBIS model are used to summarize them all. Of course, such an analysis can be accepted at a lower frequency, but for higher-frequency signals and more accurate simulation, it is not precise enough. Now there is a trend to use the V-I and V-T curves of the IBIS to describe the characteristics of the Buffer, and use the SPICE model to describe the package parameters.
The influence of wiring topology on signal integrity
When signals are transmitted along transmission lines on high-speed PCB boards, signal integrity problems may occur. The influence of the wiring topology on signal integrity mainly reflects that the arrival time of signals at each node is inconsistent, and the arrival time of reflected signals at the same node is also inconsistent, resulting in deterioration of signal quality. Generally, a star topology can achieve better signal quality by controlling several branches of the same length to make the signal transmission and reflection delay consistent.
Before using the topology, it is necessary to consider the situation of signal topology nodes, the actual working principle, and the difficulty of wiring. Different Buffers have different effects on signal reflection, so the star topology cannot solve the delay of data address buses connected to FLASH and SDRAM very well, and then the signal quality cannot be ensured; on the other hand, high-speed signals generally communicate between DSP and SDRAM, and the rate when FLASH is loaded is not high, so in high-speed simulation, only the waveform at the node where the actual high-speed signal works effectively needs to be paid attention to, without paying attention to the waveform at the FLASH; compared with the daisy chain topology, the star topology is more difficult to wire, especially when a large number of data address signals adopt the star topology.
RF wiring, choose via or bending wiring
Analyze the return path of RF circuits, which is different from the signal return in high-speed digital circuits. They have something in common, that is, they are distributed parameter circuits, and the characteristics of the circuits are calculated using Maxwell's equation. But RF circuits are analog circuits, and in some circuits, both voltage V = V(t) and current I = I(t) need to be controlled, while in digital circuits, only the change of signal voltage V = V(t) is concerned. Therefore, in RF wiring, in addition to considering the signal return, it is also necessary to consider the impact of wiring on the current. That is, whether bending wiring and via have an impact on the signal current.
In addition, most RF boards are single-sided or double-sided PCBs, and there is no complete planar layer. The return path is distributed on various grounds and power supplies around the signal. When simulating, 3D field extraction tools need to be used for analysis, and at this time, the return of bending wiring and via needs to be analyzed specifically; high-speed digital circuit analysis generally only deals with multi-layer PCBs with complete planar layers, using 2D field extraction analysis, only considering the signal return on adjacent planes, and the via is only treated as a lumped parameter R-L-C.
How to suppress electromagnetic interference
PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products.
If attention is paid to EMC/EMI in high-speed PCB design, it will help shorten the product research and development cycle and accelerate the product listing time.
The three elements of EMC are the radiation source, the transmission path, and the victim. The transmission path is divided into space radiation transmission and cable conduction. So to suppress harmonics, first look at the way it spreads. Power decoupling is to solve the conduction method of transmission, and in addition, necessary matching and shielding are also required.
Filtering is a good way to solve EMI radiated through the conduction path. In addition, it can also be considered from the aspects of the radiation source and the victim. In terms of the radiation source, try to use an oscilloscope to check whether the signal rising edge is too fast, there is reflection or Overshoot, Undershoot or Ringing, if so, matching can be considered; in addition, try to avoid signals with a 50% duty cycle, because this kind of signal has no even harmonics, and there are more high-frequency components. In terms of the victim, measures such as ground wrapping can be considered.
