One of the primary goals for the power supply industry is to bring higher power conversion efficiency and power density to power devices in applications such as data centers and 5G. Integrating a driver circuit and power MOSFET—known as a DrMOS—into an IC increases power density and efficiency when compared to a conventional, discrete MOSFET with an individual driver IC.
Moreover, DrMOS’s flip-chip technology further optimizes the voltage regulator’s performance by reducing response time and reducing the inductance between the die and package (Figure 1).
Figure 1 Here is a comparison between conventional wire bond and flip-chip technology.
However, parasitic inductance on the substrate and PCB significantly impacts the drain-to-source voltage (VDS) spike, and that’s due to resonance between parasitic inductance and MOSFET’s output capacitance (COSS). A high VDS spike can cause a MOSFET avalanche, which leads to device degradation and reliability issues. To prevent an avalanche breakdown on the MOSFET, there are several methods to alleviate voltage stress.
The first method is to apply a higher-voltage, double-diffused MOSFET (DMOS) process on the DrMOS. If this process is adopted in the power MOSFET design, it results in a higher on resistance (RDS(ON)) for the DrMOS due to a reduced number of paralleled DMOS within the same space.
The second method is to use a snubber circuit to suppress voltage spike. However, this method leads to extra loss on snubber circuit. Furthermore, adding a snubber circuit may not effectively lower the MOSFET’s VDS spike since the stray inductance that causes resonant behavior is mainly integrated in DrMOS’s package.
When trying to increase voltage regulator efficiency and reduce the MOSFET’s voltage spikes, the tradeoffs described above can make it difficult to quantify and optimize the effects of parasitic inductance on the PCB and substrate.
This article will first discuss parasitic inductance modeling. Next, the equivalent parasitic circuit model is applied in a SPICE simulation tool to predict the VDS switching spike. Experimental results will be presented to verify the feasibility of the parasitic model.
Parasitic inductance modeling on a DrMOS
To model parasitic inductance, 3D structures of both the DrMOS and PCB were built for a simulation analysis (Figure 2). Parameters such as the material, stack-up information and PCB as well as package layer thickness are crucial for modeling accuracy.
Figure 2 DrMOS and PCB’s 3D-modeling structure can be used to obtain parasitic inductance.
After 3D-modeling the PCB and DrMOS, the parasitic inductance can be characterized and obtained via ANSYS Q3D extractor. Since this article focuses on the MOSFET’s VDS spike, the main simulation settings of interest are the parasitic parameters on the power nets and driver nets.
When considering the parasitic component obtained from Q3D extractor, the parasitic inductance matrix—including the self and mutual terms of each net on the DrMOS—can be selected under different frequency conditions. Since the resonant frequency for VDS on the high-side MOSFET (HS-FET) and low-side MOSFET (LS-FET) is between 300 MHz and 500 MHz, the parasitic inductance matrix under 300 MHz condition is adopted for further behavior model simulation.
Behavior model simulation on SPICE
After the equivalent parasitic component model is exported from Q3D, the effects of different types of decoupling capacitors on the PCB are taken into account. Due to the capacitance decay after applying a DC voltage on a multi-layer ceramic capacitor (MLCC), it’s important to consider the equivalent circuit of each individual MLCC under certain DC voltage bias conditions. Each consideration should be based on the MLCC’s operating voltage. Figure 3 shows the circuit configuration for the behavior model simulation on SPICE.
Figure 3 A circuit can be configured with a behavior model simulation.
Table 1 shows the simulation and measurement conditions based on the schematic shown in Figure 3.
Table 1 The data shows the results of experimental test bench. Source: Monolithic Power Systems
Optimizing parasitic inductance
To suppress VDS spike without compromising efficiency, it’s vital to optimize parasitic inductance on the PCB and package. With advanced package technology, input capacitors can be integrated in the package to shorten the decoupling path (Figure 4). Paralleling the embedded capacitors in the package can effectively reduce the equivalent parasitic inductance on the DrMOS.
Figure 4 A 3D DrMOS structure with embedded capacitors optimizes the VDS spike.
Table 2 shows the equivalent parasitic inductance and VDS spike when utilizing different decoupling capacitor configurations on DrMOS.
Table 2 Equivalent parasitic inductance and VDS spike are shown with different capacitor configurations.
As the simulation results in Table 2 show, not only is the equivalent parasitic inductance lowered, but the VDS spike on MOSFET is also suppressed. Moreover, thanks to the MLCC’s low-ESR characteristics, no additional power loss is generated on the embedded input capacitors. Therefore, it’s possible to add different embedded input capacitors to reduce parasitic inductance in DrMOS applications.
DrMOS with embedded capacitors
This article has explained the effect of parasitic inductance on the VDS switching spike, as well as several methods to prevent an avalanche breakdown on the MOSFET due to the VDS switching spike. To quantify the effects of parasitic inductance on the VDS switching spike, parasitic inductance modeling is first introduced, and then behavior modeling on SPICE is proposed.
The results obtained via SPICE closely matched the experimental results for DrMOS solutions such as the MP87000-L, which means the behavior model can accurately predict the risk of an avalanche breakdown on the MOSFET.
To effectively suppress the VDS spike without any tradeoffs, embedded capacitors in the package were introduced. The behavior model simulation confirmed that these capacitors can reduce the equivalent parasitic inductance, and thus lower the VDS spike without additional loss.