Circuit board design is a critical and time-consuming task, and any problems that arise require engineers to examine the entire design, network by network, component by component. It can be said that circuit board design requires a level of care no less than chip design.
A typical circuit board design process consists of the following steps.
The first three steps take the most time, because schematic checking is a manual process. Imagine a SoC board with 1000 or more connections. Manually checking each wire is a long and tedious task. In fact, it is almost impossible to check every single wire, which can lead to problems with the final board, such as wrong wires, suspended nodes, etc.
The schematic capture phase generally faces the following types of problems.
● Underline errors: e.g. APLLVDD and APLL_VDD
● Case-sensitive problems: e.g. VDDE and vdde
● Spelling errors
● Signal shorting problems
● And many more
To avoid these errors, there should be a way to check the whole schematic in a few seconds. This method can be implemented with schematic simulation, which is still rarely seen in the current board design process. The schematic simulation allows the final output to be observed at the required nodes, so it can automatically check all connection problems.
This is explained below with a project example.
Consider a typical block diagram of a circuit board.
Figure 1
In a complex board design, the number of connections can reach thousands, and a very small number of changes is likely to waste a lot of time to check.
Schematic simulation not only saves design time, but also improves the quality of the board and increases the efficiency of the entire process.
A typical device under test (DUT) has some of the following signals.
Figure 2
The DUT will have various signals after some pre-tuning and has various modules, such as regulators, op-amps, etc., for signal tuning. Consider an example of a supply signal obtained through a voltage regulator.
Figure 3: Schematic of the sample board.
To verify the connection relationships and perform an overall check, schematic simulation is used. The schematic simulation consists of schematic creation, testbench creation and simulation.
During the testbench creation, an excitation signal is given to the necessary inputs and then the output results are observed at the signal point of interest.
The above process can be implemented by connecting probes to the nodes to be observed. The node voltages and waveforms can indicate whether the schematic has errors or not. All signal connections are automatically checked.
Figure 4: Schematic testbed and simulation values for each node.
Let us look at a part of the above diagram, where the nodes and voltages probed are clearly visible.
Thus with the help of simulation, we can directly observe the results and confirm whether the board schematic is correct. In addition, the investigation of design changes can be achieved by carefully adjusting the excitation signal or component values. Thus schematic simulation saves a lot of time for board designers and checkers and increases the chances of correctness of the design.