Impedance Matching for High Speed Signals in PCB Design

The process for impedance matching in high speed PCB designs depends on the signaling standard, supply voltage levels, and signal levels. We often say that PCB traces should simply have 50 Ohm impedance, but this becomes more complicated when dealing with coupling between differential pairs. High speed digital designers should take time to understand this important process and design interconnects with proper termination to match their signaling standard.

Impedance Matching for Single-ended Signals

Because impedance mismatches between components, traces, and vias depend on trace geometry, logic family, and coupling, you need to carefully design traces to have the proper single-ended and differential impedance. Different logic families have signaling standards that define how a driver, trace, and receiver need to be terminated to provide consistent impedance matching in PCB interconnects. While we’ll look specifically at PCB transmission lines between integrated circuits, the same ideas apply to interconnects inside an integrated circuit, where transmission lines need to be carefully designed to ensure impedance matching.

For single-ended signals, you simply need to worry about the input impedance (for receivers) and output impedance (for drivers). Note that dispersion in the PCB substrate can complicate impedance matching, and your goal should be to adjust the geometry to ensure impedance matching throughout the signal bandwidth. This can become a complex optimization problem, which I’ve discussed elsewhere on this blog and in a few articles on Altium’s PCB Design Blog.

IC manufacturers have gotten much better about reporting the input and output impedance spectra for their components. At minimum, they should tell you the pin-package lead inductance, input capacitance, and equivalent input resistance. All these values depend on logic family. You can then use any of the standard impedance matching schemes for high speed interconnects to prevent signal reflection and ensure power transfer. The standard methods used for impedance matching in single-ended signaling standards are shown below. Note that each of these has a fly-by variation, where the termination resistor is connected directly to the component pad rather than the trace.

Differential Signaling and Impedance Matching

There are many high speed interfaces that use differential signaling. Some of these (e.g., LVDS) have high input impedance, while others have fixed input impedance. Note that some integrated circuits may have on-chip termination (e.g., high pin count LVDS devices). These high speed differential signaling standards include the following:

• LVDS (Low-Voltage Differential Signaling): High input impedance, uses a parallel resistor at the receiver to match the receiver’s input impedance to each of the 50 Ohms traces in the differential pair. For DC coupling, the simplest method is double termination, where a 100 Ohms resistance is placed across the differential terminals to match to the differential impedance of the differential pair.

• CML (Current Mode Logic): Specified input and output impedance of 50 Ohms, which is referenced to the single-ended impedance of each trace in a differential pair. CML chips may not have input termination resistors and require pull-up and pull-down resistors to match the input level to the Vdd level on the chip (see the application notes linked below).

• PECL (Pseudo-Emitter Coupled Logic): Traces have 100 ohm differential impedance and 50 Ohms single-ended impedance. Outputs have low impedance (~5 Ohms), which requires pull-up/pull-down resistors for impedance matching.

• HSTL (High Speed Transceiver Logic): There are four classes of HSTL for signaling between CMOS and BiCMOS devices, each requiring different termination methods.

• PCIe: From PCI-SIG standards, PCIe Gen1 has 100 Ohms differential impedance, and Gen2 and higher have 85 Ohms differential impedance. For PICMG COM Express designs, traces on the bus must have differential impedance of 92 Ohms (COMCDG Rev. 1.0) or 85 Ohms (COMCDG Rev. 2.0 and 3.0).

• Ethernet: Ethernet lines are differential pairs with 100 Ohms differential impedance with single-ended impedance of 50 Ohms.

• USB: 50 Ohms characteristic impedance, differential impedance matching at 90 Ohms, which matches the differential impedance of a USB cable.

 

How Coupling in Differential Pairs Affects Impedance Matching

If you look through the above list, you’ll see that the specifications state that an individual trace must have 50 Ohms single-ended impedance and 100 Ohms differential impedance. These specs are very poorly written and we need to distinguish between two different single-ended impedance values:

• Characteristic impedance (Z0): This is the impedance of a single trace above its ground plane when there are no other traces around. If only the trace and its ground plane exist on the PCB, then the trace's impedance will be the characteristic impedance.
• Odd-mode impedance: Once another trace is brought close to our original trace with characteristic impedance of Z0, and the two are driven differentially, the original trace's impedance is no longer Z0, it is the odd-mode impedance.

The odd-mode impedance value depends on the mutual capacitance and mutual inductance between the two traces. This is shown in the graphic below. In this graphic, we have a set of traces that include the mutual capacitance and the mutual inductance between them. The result is that the odd-mode impedance is always lower than the characteristic impednace.

The other formula below shows how the mutual capacitance and mutual inductance arise in my summative transmission line impedance formula (see my IEEE paper on the topic).

 

The differential impedance is just double the odd-mode impedance, or Z(diff) = 2Z(odd). If we were to design to Z(diff) = 2Z0, there is a chance we would not have optimal impedance matching for high-speed differential signals.

For a given trace width, the ratio of the characteristic impedance to the odd-mode impedance will depend on the spacing between the pair and the height of the pair above the substrate. How large does the deviation get? This is shown in the graph below. This graph shows boundary element method (BEM) simulation results comparing the characteristic impedance of one trace in a differential pair to its odd-mode impedance as a function of spacing between the traces and the height above the substrate. We can see that, when the traces are closer together, and the substrate is thicker, the characteristic impedance will be much larger than the odd-mode impedance. For example if the

 

 

This is why the word "single-ended impedance" in a differential impedance spec should not be construed to mean "characteristic impedance," it is referring to the odd-mode impedance. The way this is approached is as follows:

• Design each trace with characteristic impedance that is slightly larger than 50 Ohms, and design the pair with the same width so that the differential impedance is exactly 100 Ohms. This will set the odd-mode impedance to 50 Ohms.
• In many cases, this means that slightly larger spacing is actually desired, although the excact amount will depend on the spacing-to-height ratio for the particular stackup and material dielectric constant. The idea of "tight coupling" is not well-defined, and it is not required for a differential pair to perform its intended function.

In differential pairs, we are actually impedance matching to the odd-mode impedance value of each trace in the pair, we are not matching to some differential impedance value. The odd-mode impedance is the only impedance that matters when designing a differential pair or terminating a differential receiver. This is because the input impedance looking into each differential pin on the receiver only interacts with a single trace in the pair, and that trace's impedance is the odd-mode impedance. The impedance mismatch right at that pin will determine the amount of reflection for the incoming signal.

In simulations and measurements, the situation is quite different. In VNA measurements for example, we terminate the differential input to a specified differential impedance, which is just double the odd-mode impedance. This termination resistor exists across the VNA inputs; it is effectively applying split termination with zero offset bias. Simulations effectively mimick this by allowing the user to specify a differential termination resistance in the simulation configuration. This means that the S11 value you see from an S-parameter simulation for a differential channel is measuring the reflection of each polarity signal from half the termination resistance.

For more help with board layout, take a look at our high speed PCB design guidelines, which apply to single-ended and differential pairs in your board.