Step 1 - Prepare the Circuit Schematic
The PCB layout is based on the circuit schematic diagram which shows the electrical connectivity.
- Use EDA software like Eagle, KiCad, OrCAD, Altium etc. for drawing schematics.
- Arrange components neatly with digital parts on left and analog parts on right.
- Name each component, wire, and net as per a systematic naming convention.
- Group related components together with supply rails to make areas of the schematic.
- Add test points, debug LEDs, pull-up/pull-down resistors as needed.
- Connect any off-board components, connectors, cables in the schematic.
- Simulate and verify the schematic for functionality before PCB layout.
Step 2 - Select the Right PCB Materials
- Choose substrate material (FR-4, Rogers, polyimide, etc.) based on mechanical, electrical, thermal needs.
- Determine copper thickness – 1 oz, 2 oz or thicker copper based on current requirements.
- Calculate number of copper layers needed – 2 layer, 4 layer, 6 layer etc. in line with complexity.
- Select surface finish – HASL, immersion silver, ENIG, OSP etc. per soldering method.
- Choose solder mask color, finish – matte, glossy etc. Green and red common colors.
- Pick legend printing – negative or positive printing, font size, color.
- Specify board thickness, connector types, special coatings.
Step 3 - Placement Outline and Placement
A. Board Outline
- Draw board profile aligned with fabrication panel sizes – 12″x18″, 18″x24″, etc.
- Decide mounting holes – quantity, diameter, location suiting enclosure.
- Add any edge connectors, cable cutouts, handles, guidefins.
- Account for panelization tabs for assembly, breakoff rails.
B. Component Placement
- Place components starting with largest mechanically fixed parts.
- Arrange parts with consideration for accessibility and serviceability.
- Group components according to high speed and low speed circuits.
- Place connectors along edge for accessibility.
- Ensure clearance of parts from mounting holes and edges.
- Add inspection points, test lands, fiducials for assembly.
- Optimize placement for manufacturability and ease of assembly.
Step 4 - Floor Planning and Routing
A. Power Planes
- Define power net shapes on inner layers adjacent to signal layers.
- Allow clearance between planes for routing signals through vias.
- Add voids in planes for vias and thermal isolation needs.
- Connect planes to supplies with multiple vias for redundancy.
B. Signal Routing
- Route critical high speed traces first with controlled impedance.
- Minimize crosstalk by spacing out parallel traces based on signals.
- Use 45° and 90° angles instead of arcs for controlled impedance.
- Limit acute angles with maximum right angles for manufacturability.
- Route traces on a single layer first before changing layers.
- Verify trace widths and clearances as per fabrication rules.
Step 5 – Final Checks and Finishing Touches
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- Run design rules check and electrical rules check on completed layout.
- Review manufacturability guidelines like minimum hole size, trace spacing etc.
- Examine board for any missing connections in the schematic.
- Check for unrouted nets, unintended shorts, clearance violations.
- Confirm via stitching, back drilling for high speed signals.
- Examine decoupling capacitor placement near each IC.
- Review any redundant vias, traces overlapping pads.
- Rename nets, components as needed for readability.
Step 5 - Final Checks and Finishing Touches
- Run design rules check and electrical rules check on completed layout.
- Review manufacturability guidelines like minimum hole size, trace spacing etc.
- Examine board for any missing connections in the schematic.
- Check for unrouted nets, unintended shorts, clearance violations.
- Confirm via stitching, back drilling for high speed signals.
- Examine decoupling capacitor placement near each IC.
- Review any redundant vias, traces overlapping pads.
- Rename nets, components as needed for readability.
Step 6 - Generate Fabrication and Assembly Files
A. Gerber Files
- Export individual Gerber files – top and bottom layers, inner layers, drill file, solder mask, legend.
- Generate additional files like drill drawing, testpoints file, paste mask.
- Confirm files are formatted correctly and not mirrored or inverted.
B. Assembly Files
- Output BOM in csv format for components, reference designators, quantities.
- Export centroid or placement file from CAD software.
- Create pick and place file with rotation and side details.
- Generate stencil file for solder paste application.
Step 7 - Panelization for Board House
- Arrange multiple PCBs together within the panel for fabrication.
- Add mouse bites, breakaway tabs, fiducials, test coupons.
- Ensure adequate spacing between boards for cutting and routing.
- Check for exposed copper or traces along panel edges.
- Confirm panel dimensions align with board house requirements.
- Adjust layout to avoid any exposed board edges post breakoff.
Step 8 - Final Design Review and Artwork Submission
- Complete design review with PCB designer’s checklist as signoff.
- Have your layout reviewed by an experienced PCB designer.
- Submit Gerber files zipped in a folder along with readme documentation.
- Share BOM, centroid and placement files for assembly separately.
- Keep a backup copy of all files before submission.
Tips for Advanced PCBs
For high complexity boards:
- Model layout in 3D for visualizing fit and assembly.
- Perform signal and power integrity analysis through simulation.
- Account for controlled impedance traces and length matching.
- Incorporate thermal analysis of critical hot components.
- Implement EMI/EMC techniques – stitching vias, shielding etc.
- Design for reliability using redundancy, derating, and testing points.
Common Design Mistakes to Avoid
Schematic Errors
- Unconnected pins, missing power connections.
- Net name mismatches between schematic and PCB.
- Simulation not capturing actual circuit behavior.
Layout Errors
- Inadequate clearance between traces and pads.
- Acute trace angles. Long, unrouted traces.
- Too many vias in pads reducing solderable area.
- No provision for mounting or enclosure.
Manufacturability Issues
- Trace/space smaller than fabrication capability.
- Annular rings around pads insufficient.
- Placing via under BGA causing assembly issues.
- No provision for thermal relief, stitching vias.
Documentation Errors
- Incorrect layer order in fabrication drawings.
-BOM not matching with reference designators.
- Important instructions missing from readme.