RF board PCB layout principles
Before starting the layout, make sure you understand the board's function, working frequency band, current and voltage, key RF device kinds, EMC, and related RF indicators, as well as the stack structure, impedance control, external structure size, shielding cavity, and cover size. Location, unique device processing instructions (such as hollowing out, device size and position for direct chassis heat dissipation), and so on. In addition, the main RF device's power, heat dissipation, gain, isolation, sensitivity, and other indications, as well as the filtering, biasing, and matching circuits' connections, should be provided. The matching routing requirements indicated in the device documentation or the RF field analysis software simulation for the power amplifier circuit Impedance matching circuit guidelines were obtained.
Physical partition: The key is to organize the main components in accordance with the single board's main signal flow legislation. Except for the common layout, fix the components on the RF path according to the position of the RF port and change their orientation to minimize the length of the RF path. To provide sufficient isolation of various circuits, it is also required to consider how to eliminate mutual interference and anti-interference ability of each portion, in addition to the regulations. Consider utilizing a metal shield to shield the RF in circuit modules with poor isolation or sensitive and intense radiation sources. In the RF area, the energy is shielded.
The electrical partition divides the plan into three sections: power supply, digital, and analog. It must be space separated, and the layout and wiring must not overlap areas. Additionally, try to distinguish between strong and weak current signals, as well as between digital and analog signals. As far as practical, circuits that perform the same function should be grouped within a particular range, lowering the signal loop area.
RF transmission line
To transport RF power to (or from) IC pins on the PCB, many Maxim RF components require impedance-controlled transmission lines. These transmission lines might be hidden in the inner layers or implemented in the outside layers (top or bottom layers). Microstrip, stripline, coplanar waveguide (ground), and characteristic impedance are all discussed in this guide to transmission lines. Transmission line bend angle adjustment and transmission line transitions are also introduced.
Microstrip line
A fixed-width metal trace (conductor) plus a ground space just below make up this sort of transmission line (adjacent layers). Traces on layer 1 (top metal), for example, necessitate a solid ground region on layer 2. (Figure 1). The characteristic impedance (typically 50 or 75) is determined by the width of the trace, the thickness of the dielectric layer, and the kind of dielectric.
Stripline
Fixed-width traces on inner layers, as well as ground surfaces above and below, are examples of such lines. The conductors can be at the center of the ground area (Fig. 2) or displaced slightly (Fig. 3). For RF traces on the inner layer, this approach is appropriate.
Coplanar waveguide (Ground)
Coplanar waveguides offer improved isolation between nearby RF lines and other signal lines (end view). A center conductor and ground portions on both sides and below make up this medium (Figure below).
Installing "fences" on both sides of the coplanar waveguide is recommended, as seen in Figure below. Installing a row of ground vias in the top metal ground section on each side of the intermediate conductor is demonstrated in this top view. The ground plane below is shorted by the loop current created on the top layer.
Impedance characteristic
To accurately select the signal conductor line width to obtain the intended impedance, several calculation tools (the Polar SI9000, a PCB characteristic impedance calculator recommended) can be employed. When inputting the dielectric constant of the board layers, however, caution is advised. The dielectric constant is lower because the outside substrate layer of a typical PCB includes less glass fiber than the inner layer. The dielectric constant of FR4 material, for example, is R = 4.2, while the dielectric constant of the outer substrate (prepreg) layer is R = 3.8.
Compensation for bending transmission lines
Use a bend radius at least 3 times the width of the intermediate conductor when the transmission line must bend (change direction) owing to routing constraints. That is to say:
The radius of bending is 3 millimeters (line width)
This reduces the corners' typical impedance variation.
If a progressive bend is not practicable, the transmission line can be bent at an angle (rather than curved), as seen in Figure 6. However, to lessen the impedance abrupt shift produced by the increase in the local effective line width when passing through the inflection point, this must be corrected for. Corner miter is the most common compensating method, as indicated in the diagram below. The Douville and James formula determines the best microstrip right-angle miter:
M is the ratio (percentage) of mitered and non-metered bends in the formula. Subject to the requirement that w/h 0.25, this formula is independent of the dielectric constant.
Other transmission lines can benefit from similar techniques. If the correct compensation mechanism is unknown and the design calls for a high-performance transmission line, the corners should be modeled using an electromagnetic simulator.
Layer change of transmission line
If layout restrictions force transmission lines to be shifted to separate board layers, at least two vias per transmission line are recommended to reduce via inductive loading. A pair of vias reduces transmission inductance by 50%, and the greatest diameter vias that are proportional to the transmission line width should be employed. The through diameter (polish plating diameter) for a 15-mil microstrip line, for example, should be 15 mil to 18 mil. If there isn't enough room for huge vias, three smaller transition vias should suffice.
Signal line isolation
Accidental coupling between signal lines must be avoided at all costs. Here are some examples of possible couplings and precautions:
Transmission lines for RF signals: Transmission lines should be spaced as far apart as possible and should not be too close to each other across long distances. The greater the coupling between parallel microstrip lines, the closer they are to each other and the longer the gap between parallel traces. Ground planes should be used to isolate traces on different layers. High-power transmission lines should be kept as far apart as feasible from other transmission lines. Line-to-line isolation is strong with grounded coplanar waveguides. It's impossible to get better than -45dB isolation between RF lines on a tiny PCB.
High-speed digital signal lines: To avoid coupling, these signal lines should be routed on a separate circuit board layer from the RF signal lines. Digital noise (from clocks, PLLs, and other sources) links into RF signal lines, modulating the RF carrier. Alternatively, digital noise may be upconverted or downconverted in some circumstances.
VCC/Power Lines: Dedicated layers should be used to route these lines. At both the main VCC distribution node and the VCC branch, appropriate decoupling/bypass capacitors should be placed. The frequency response of the RF IC as a whole, as well as the expected frequency distribution of digital noise due to clocks and PLLs, must be considered while selecting bypass capacitors. These traces should also be maintained separate from the RF lines, which will be emitting a lot of RF energy.
Grounded area
If RF components and transmission lines are utilized on layer 1, a solid (continuous) ground area on layer 2 is recommended. Ground areas above and below the intermediate conductor are necessary for stripline and offset stripline. These areas must be totally assigned to the ground, not shared or assigned to signal or power networks. A local ground region on a layer may exist owing to design constraints and must be situated underneath all RF components and transmission lines. Under the transmission line, the ground area must not be broken.
Between separate layers of the RF area of the PCB, a high number of ground vias should be inserted. This reduces parasitic ground inductance by preventing ground current loops. Vias also prevent RF signal lines from cross-coupling with other signal lines on the PCB.
Special considerations for power and ground planes
The component loop current must be considered for circuit board layers assigned to system power (DC power) and ground. The general practice is to avoid routing signal lines between the power and ground planes on board layers.
Power (bias) traces and power supply decoupling
When a component has numerous power connections, it's customary to employ a "star" power routing setup (Figure 9). Install larger decoupling capacitors (tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of tens of The value of these tiny capacitors is determined by the RF IC's operating frequency and purpose (ie, interstage decoupling from mains). An example can be seen in the image below.
When compared to a configuration in which all pins connected to the same power net are connected in series, the "star" layout avoids long ground loops. Long ground loops will result in parasitic inductances, which might lead to unintended feedback loops. The DC power supply must be electrically connected as AC ground, which is an important aspect for power supply decoupling.
Decoupling and bypass capacitor selection
The effective frequency range of capacitors is limited in reality due to the presence of self-resonant frequencies (SRFs). SRFs can be obtained from the manufacturer, however direct measurement characterization is occasionally required. Capacitors have no decoupling or bypass function above SRF since they are inductive. It is normal practice to employ many (capacitance) rising capacitors in parallel if broadband decoupling is required. Small capacitors have a higher SRF (for example, SRF = 14GHz for a 0.2pF, 0402 SMT package capacitor), while bigger capacitors have a lower SRF (for example, SRF = 4GHz for a 2pF capacitor in the same package).
Bypass capacitor layout considerations
Because the power lines must be AC ground, it's critical to keep the AC ground loop's parasitic inductance to a minimum. Parasitic inductance can be caused by component placement or orientation, such as the ground direction of decoupling capacitors. As shown in Figures 10 and 11, there are two approaches for placing bypass capacitors:
The vias connecting the VCC pads on the top layer to the inner power regions (layers) can interfere with the AC ground current return path in this layout, resulting in a longer return path and higher parasitic inductance. Any AC current flowing into the VCC pin passes through the bypass capacitor to its ground side before returning to the internal ground plane. The total footprint of the bypass capacitors and accompanying vias is minimized in this setup.
The AC ground return is not constrained by vias in the power area in another design. This design necessitates a somewhat larger PCB area in general.
Grounding of the short-circuit connecting element
It is advised to utilize at least two ground vias per component for shunt-connected (grounded) components, such as power supply decoupling capacitors, to minimize the effects of parasitic inductance (Figure 12). Vias to the ground can be used to "island" groups of short-connected components.
IC ground area ("pad")
Most ICs require a solid ground space just below the component on the component layer (top or bottom of the PCB). The DC and RF return flow will be carried through the PCB to the designated ground region by this ground area. The second purpose of the component's "ground pad" is to act as a heat sink, hence the pad should have as many vias as the PCB design regulations allow. An array of 5 5 vias is put in the intermediate ground area (on the component layer) just below the RF IC in the example illustrated below (Figure 13). Where other layout considerations allow, the maximum number of vias should be used. These are excellent vias (penetrating the entire PCB). These vias will need to be plated. Fill the vias with thermal paste if possible to increase thermal performance (fill the thermal paste after plating the vias and before finally plating the board).
Shield cover
The isolation of metal between two geographical areas known as PCB shielding is used to control the induction and radiation of electric fields, magnetic fields, and electromagnetic waves from one place to another. To prevent the interference electromagnetic field from spreading out, surround the interference source of components, circuits, assemblies, cables, or the entire system with a PCB shield; surround the receiving circuit, equipment, or system with a PCB shield to prevent them from being affected by the external electromagnetic field.
Several wiring layout details
1. The RF link is described in a single word. When the pattern is in the same shielding cavity, it can be placed in a single word and in a L shape depending on the signal size, which ranges from tiny to large. Between strong and weak signals, shielding and isolation should be applied, and shielding measures should also be taken on the branch with the higher gain. Avoid using Z-shaped, U-shaped, or crossover layouts in the same shielding cavity.
2. A three-resistor PI-type attenuator can be installed on the microstrip line during layout and cannot be bent, as illustrated in Figure 1. If there isn't enough room on the layout, the two grounding resistors must be placed on the shortest high-resistance branch line possible.
3. The feeding inductor of the bias circuit should not be parallel to the RF channel, but rather perpendicular to it.
4. Keep the high-power RF transmitting circuit separate from the low-power RF receiving circuit by isolating the high-power RF amplifier (HPA) and the low-noise amplifier (LNA) as much as feasible.
5. To prevent the output signal from being connected to the input terminal, the RF output terminal should be kept as far away from the RF input terminal as practicable.
6. The decoupling capacitor is close to the device to be protected, and the ESD-sensitive device's decoupling capacitor should be close to the device's power and ground pins.
7. The filter output end should be as close to the voltage control input end of the voltage-controlled oscillator (VCO) as practicable, and the layout should be based on the minimal process interval.
8. The attenuator network is utilized to improve the dielectric filter's port matching. It should be close to the dielectric filter's port; otherwise, the filter's port will be severely mismatched out of the band, resulting in significant reflection. It may induce out-of-band self-excitation after being cascaded with the amplifier.
9. The shield's inner wall should be at least 1MM wide. The device pads in the cavity should be at least 2mm away from the cavity's edge, and other signals should be at least 0.5mm away from the cavity's edge. Add fixed mounting holes at the cavity's corners, which should be 2.8-3mm in diameter.
10. As much as possible, keep digital circuits away from analog circuits, ensure that the RF traces relate to a large ground plane, and run the RF traces on the surface.
11. There are no digital or analog signal lines that traverse areas. If the RF wiring must pass through the signal line, it is preferable to route a layer of ground connected to the main ground between them; the other option is to ensure that the RF wiring crosses the signal lines to minimize capacitive coupling while placing as much ground as possible around each RF trace and connecting to the main ground. RF printed lines should not be wired in parallel and should not be excessively long in general. A ground wire should be inserted between the two lines if parallel wiring is truly required (the ground wire should be drilled through holes to ensure good grounding). RF differential line, parallel lines, ground lines outside the two parallel lines (ground lines are drilled through holes to provide good grounding), and the printed lines' characteristic impedance is developed to meet the device's needs.
12. The following is the basic RF printed circuit board wiring sequence: Baseband of an RF line Clock line power supply portion digital baseband part ground RF interface line (IQ line)
13. Because green oil will affect the performance and signal of the microstrip line, it is advised that higher frequency microstrip lines not be coated with green oil, while medium and low-frequency single-board microstrip lines should be coated with green oil.
14. Most RF traces are not pierced. If the RF traces must be replaced, the size of the vias should be kept to a minimum to avoid path inductance and the risk of RF energy leaking to other sections of the laminate.
15. In the duplexer, intermediate frequency amplifier, and mixer, there are always several RF/IF signals conflicting with each other. The RF and IF traces should be crossed as much as feasible, with a ground in the middle.
16. Extending the surplus wire ends on the RF signal traces is prohibited unless for particular purposes;
17. The baseband RF interface line (IQ line) wiring should be wider, ideally greater than 10 mils. The line length should be as equal as feasible, and the spacing should be as equal as possible, to avoid phase inaccuracy.
18. To avoid the introduction of noise, the RF control line requires the wire to be as short as feasible, and the wiring length is regulated according to the input and output impedance of the transmission control signal device. RF signals, non-metalized vias, and "ground" edges should all be kept away from traces. To prevent signals from being linked to the RF ground through the vias, do not drill ground vias around the traces.
19. As far as possible, keep digital and power wiring away from RF circuits; clock and high-frequency circuits are the principal sources of interference and radiation, and must be placed separately and away from sensitive circuits.
20. The main clock wiring must be as short as feasible, with a line width of at least 10 microns and both sides of the trace grounded to prevent interference from other signal lines. For routing, it is recommended that you utilize the stripline form.
21. There are no digital or analog signal lines that span areas. Layered wiring is preferred if the signal lines must pass through the RF lines, and a ground plane connected to the main ground is routed along the RF lines between them; the RF and signal lines cross, and the digital signal with lower frequency can pass vertically between the large package capacitor pads. At the same time, as much ground as feasible is dispersed and connected to the main ground around each RF trace. Inductive coupling is also reduced by reducing parallel lengths between RF traces.
22. The control line of the voltage-controlled oscillator (VCO) must be kept away from the RF signal, and the VCO control line can be subjected to packet processing if necessary;
23. Place as many grounds as possible on each layer of the PCB board and connect them to the main ground. To enhance the number of graphs for the internal signal and power distribution layers, place traces as near together as feasible.
24. Impedance: The RF line has a 50-ohm impedance, so the line width should be as wide as feasible to match the impedance requirements. The line width should be as near to the 0603 resistive device's size as practicable.
25. Corner: When the RF signal trace is at a right angle, the effective linewidth at the corner increases, the impedance becomes discontinuous, and reflection occurs. As a result, corner processing can be separated into two categories: chamfering and rounding.
26. Gradient line: Some RF devices have small packaging, with SMD pads as small as 12 microns and RF lines as wide as 50 microns. Gradient lines are suggested, while abrupt changes in line width are not permitted.
27. Avoid punching holes in the ground for RF transmissions. If you need to punch holes and change layers, you'll need to have RF engineers simulate the aperture size. At the same time, the via hole's impedance discontinuity is minimized. Using a diskless process, selecting a good outflow method, and optimizing the diameter of the anti-pad are all common methods.
28. The vias under the large-area pads of the RF device have a maximum spacing of about /10 and a minimum spacing of about /60. A big amount of ground copper should be deposited in the blank area of the RF area, the copper should be fully connected, and vias should be provided on the ground copper. Place grounded vias in the areas where the shielding cavity walls are close together. There must be more than two rows of vias, with a via spacing of less than /20.
29. Microstrip wiring: To build a microstrip structure, the top layer of the PCB must carry the RF signal, and the plane layer below the RF signal must be completely grounded.
30. The microstrip line's edge should be at least 3W wide from the ground plane's edge below. Within the 3W range, no non-ground vias are permitted.
31. The distance from the microstrip line to the shielding wall should be kept above 2W. At least 20mil.
32. Ground copper skin should be applied to non-coupled microstrip lines in the same layer, and ground vias should be added to the ground copper skin. The holes are evenly spaced and have a hole spacing of less than /20. Sharp burrs are not allowed on the edge of the ground copper foil, which should be smooth and flat. The edge of the ground-clad copper skin should be greater than or equal to the width of 2W or 3H from the microstrip line's edge, where H denotes the thickness of the microstrip substrate medium.
33. RF signal traces are not allowed to traverse the second layer's ground plane gap.
34. Stripline wiring: RF signals must pass through the center layer of the PCB, usually from the third layer, and the second and fourth layers must be completely grounded, resulting in an eccentric stripline structure.
35. The stripline's margins on both sides should be at least 3W wide from the edge of the upper and lower ground planes, with no non-grounded vias within that range.
36. Ground copper skin should be applied to the strip lines in the same layer, and ground vias should be attached to the ground copper skin. The hole spacing is smaller than /20, and they are equally distributed. Sharp burrs are not allowed on the edge of the ground copper foil, which should be smooth and flat. The edge of the ground-clad copper skin should be greater than or equal to the width of 2W or 3H from the stripline's edge, where H denotes the entire thickness of the stripline's upper and lower dielectric layers.
37. If the stripline needs to transmit high-power signals, the copper sheets of the upper and lower reference planes in the stripline area are normally hollowed down to avoid the 50-ohm line width being too narrow, and the hollowing width is the stripline's total width. If the line width still does not satisfy the requirements after more than 5 times the thickness of the medium, hollow out the upper and lower adjacent reference surfaces of the second layer.