In circuit board design, the earlier signal integrity (SI) issues are addressed, the more efficient the design will be, thereby avoiding the need to add termination devices after the circuit board design is completed. There are many tools and resources for SI design planning. Now we explore the core issues of signal integrity and several methods to solve SI problems.
1. Raising SI questions
As IC output switching speeds increase, almost all designs encounter signal integrity issues regardless of the signal period. Even if you have not encountered SI problems in the past, as the operating frequency of circuits increases, you will definitely encounter signal integrity problems in the future.
Signal integrity problems mainly refer to signal overshoot and damped oscillation phenomena, which are mainly functions of IC drive amplitude and transition time. That is, even if the wiring topology does not change, as soon as the chip speed becomes fast enough, the existing design will become critical or stop working. We use two examples to illustrate that signal integrity design is inevitable.
One example: In the field of communications, cutting-edge telecommunications companies are producing high-speed circuit boards (above 500MHz) for voice and data exchange. At this time, cost is not particularly important, so multi-layer boards can be used as much as possible. Such a circuit board can be fully grounded and easily form a power loop. It can also use a large number of discrete termination devices as needed, but the design must be correct and cannot be in a critical state.
SI and EMC experts perform simulations and calculations before wiring. The board design can then follow a very strict set of design rules and, where in doubt, add termination devices to gain as much SI safety as possible. Margin. During the actual operation of the circuit board, some problems will always occur. For this reason, SI problems can be avoided by using controlled impedance terminal wiring. In short, super-standard design can solve SI problems.
Example 2: Considering cost, circuit boards are usually limited to four layers (the two layers are the power layer and the ground layer). This greatly limits the role of impedance control. In addition, fewer wiring layers will aggravate crosstalk, and the spacing between signal lines must be minimized to allow more printed lines to be laid out. On the other hand, design engineers must use the latest and greatest CPU, memory and video bus designs, and these designs must consider SI issues.
Engineers can usually get a lot of advice from the CPU manufacturer regarding routing, topology, and terminated pipelines; however, it is necessary for these design guidelines to be integrated into the manufacturing process. To a large extent, the circuit board designer's job is more difficult than that of the telecommunications designer because there is little room for adding impedance control and termination devices. At this time, it is necessary to fully study and solve those incomplete signals while ensuring the product design deadline.
The following introduces the general SI design guidelines for the circuit board design process.
2. Preparation work before circuit board design
Before starting the design, it is necessary to think about and determine the design strategy in order to guide work such as component selection, process selection, and circuit board production cost control. As far as SI is concerned, pre-investigation should be conducted to formulate planning or design guidelines to ensure that the design results do not have obvious SI problems, crosstalk or timing problems. Some design guidelines can be provided by IC manufacturers. However, the guidelines provided by the chip supplier (or the guidelines you design yourself) have certain limitations. According to such guidelines, it may not be possible to design a circuit board that meets the SI requirements. If design rules were easy, there would be no need for design engineers.
Before the actual wiring, you must first solve the following problems. In most cases, these problems will affect the circuit board you are designing (or are considering designing). If the number of circuit boards is large, this work is valuable.
3. Lamination of circuit boards
Some project teams have a lot of autonomy in determining the number of PCB layers, while other project teams do not have this autonomy. Therefore, it is important to understand where you stand. Talking to a manufacturing and cost analysis engineer can determine board stack-up errors, which is also a good opportunity to discover board manufacturing tolerances. For example, if you specify that a certain layer has 50Ω impedance control, how does the manufacturer measure and ensure this value?
Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on a circuit board? What is the allowable error for line width and spacing? What is the allowable error in thickness and spacing between ground and signal layers? All this information is available during the pre-wiring phase.
Based on the above data, you can choose to layer. Note that almost every PCB that plugs into other boards or backplanes has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for the different types of layers they can make, which will greatly constrain the final stackup number. . You may be tempted to work closely with the manufacturer to define the number of stacks. Impedance control tools should be used to generate target impedance ranges for different layers, making sure to take into account manufacturing tolerances provided by the manufacturer and the effects of adjacent routing.
In an ideal world for signal integrity, all high-speed nodes should be routed on impedance-controlled inner layers (such as stripline), but in practice, engineers must often use outer layers for routing all or part of the high-speed nodes. To optimize SI and keep the board decoupled, ground/power planes should be placed in pairs whenever possible. If you can only have one pair of ground/power planes, you're stuck. If there is no power plane at all, by definition you may have an SI problem. You may also encounter situations where it is difficult to simulate or emulate the performance of a board without defining the return path for the signal.
4. Crosstalk and impedance control
Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. Coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel routing length) between signal lines or between various types of signal lines. For example, if you want to limit the crosstalk from the clock to the data signal node to less than 100mV but keep the signal traces parallel, you can use calculations or simulations to find the minimum allowable spacing between signals on any given wiring layer. Also, if the design contains nodes where impedance is important (either clocks or specialized high-speed memory architectures), you must place the routing on one layer (or several layers) to get the desired impedance.
5. Important high-speed nodes
Delay and skew are key factors that must be considered in clock routing. Because of strict timing requirements, such nodes typically must use termination devices to achieve optimal SI quality. Determine these nodes up front and plan for the time required to adjust component placement and routing to adjust the design parameters for signal integrity.
6. Circuit board technology selection
Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple? Does the signal come out of the board or does it stay on the same board? What is the allowed skew and noise margin? As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for a 50MHz clock to have a 500ps rise time. A 2-3ns slew rate control device needs to be fast enough to ensure the quality of SI and help solve problems such as synchronized switching of outputs (SSO) and electromagnetic compatibility (EMC).
The advantages of driver technology can be found in new FPGA programmable design technologies or user-defined ASICs. With these custom or semi-custom devices, you have a lot of leeway in choosing drive amplitude and speed. Early in the design process, meet FPGA or ASIC design time requirements and determine appropriate output selections, including pin selections if possible.
At this design stage, a suitable simulation model is obtained from the IC supplier. In order to effectively cover SI simulations, you will need an SI simulation program and corresponding simulation model (probably an IBIS model).
Finally, you should establish a series of design guidelines during the pre-routing and routing phases, including: target layer impedance, routing spacing, preferred device process, critical node topology, and termination planning.
7. Circuit board pre-wiring stage
The basic process of pre-wired SI planning is to first define the input parameter range (drive amplitude, impedance, tracking speed) and possible topology range (min/max length, stub length, etc.), then run every possible simulation combination, analyze the timing and SI simulation results, and finally find an acceptable value range.
Next, interpret the scope of work as the routing constraints for PCB routing. Different software tools can be used to perform this type of "cleaning" preparation, and routing programs can automatically handle these routing constraints. For most users, timing information is actually more important than SI results. The results of interconnect simulation can change the wiring to adjust the timing of the signal path.
In other applications, this process can be used to identify pins or device layouts that are incompatible with system timing pointers. At this point, it is possible to completely determine which nodes require manual routing or which do not require termination. For programmable devices and ASICs, the output driver selection can also be adjusted at this time to improve the SI design or avoid the use of discrete termination devices.
8. SI simulation after circuit board layout
Generally speaking, SI design guidance rules are difficult to ensure that no SI or timing problems will occur after the actual wiring is completed. Even if the design is guided by guidelines, unless you can continuously and automatically check the design, there is no guarantee that the design fully adheres to the guidelines, and problems will inevitably occur. Post-layout SI simulation inspection will allow for planned breaking or changing of design rules, but this is only necessary for cost considerations or strict wiring requirements.
Now, with the SI simulation engine, it is possible to simulate high-speed digital PCBs and even multi-board systems, automatically masking SI issues and generating accurate "pin-to-pin" delay parameters. As long as the input signal is good enough, the simulation results will be equally good. This makes the accuracy of device models and circuit board manufacturing parameters critical factors in determining simulation results. Many design engineers will simulate the "minimum" and "maximum" design corners and use the relevant information to solve problems and adjust productivity.
9. Circuit board manufacturing stage
Taking the above measures can ensure the SI design quality of the circuit board. After the circuit board is assembled, it is still necessary to place the circuit board on the test platform and use an oscilloscope or TDR (time domain reflectometer) to measure the real circuit board and the simulated circuit board. Compare the expected results. These measurements can help you improve your model and manufacturing parameters so you can make better (less constrained) decisions during your next pre-design study.
10. Model selection
Much has been written about model selection, and engineers performing static timing verification may have noticed that despite all the data available from the device data sheet, it is still difficult to build a model. The SI simulation model is just the opposite. It is easy to establish the model, but it is difficult to obtain model data. Essentially, the only reliable source of SI model data is the IC supplier, who must maintain tacit cooperation with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need to drive market demand for this investment, and circuit board manufacturers may be the only demand-side market. .
11. Future trends in circuit board technology
Imagine that all outputs in the system can be adjusted to match the wiring impedance or the load of the receiving circuit. Such a system is easy to test. SI problems can be solved through programming, or the circuit board can be adjusted according to the specific process distribution of the IC to make the SI meet the requirements. Enables greater design tolerance or a wider range of hardware settings.
At present, the industry is also paying attention to a kind of SI device technology. Many of these technologies include designed termination devices (such as LVDS) and automatic programmable output intensity control and dynamic automatic termination functions. Circuit board designs using these technologies can obtain excellent SI quality, however, most technologies are too different from standard CMOS or TTL logic circuits and do not work well with existing analog models.
Therefore, EDA companies are also joining the circuit board design arena. People have done a lot of work to solve SI problems in the early stage of design. In the future, SI problems will be solved with the help of automated tools without SI experts. Although the current technology has not yet developed to that level, people are exploring new design methods. Starting from "SI and timing wiring", the technology of circuit board design is still developing, and it is expected that new circuit board design technology will be born in the next few years.